SH7055S Datasheet, PDF (391/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Channel 1: Channel 1 has two 16-bit free-running counters (TCNT1A and TCNT1B), eight 16-bit
general registers (GR1A to GR1H), and a 16-bit output compare register (OCR1).
TCNT1A and TCNT1B are up-counters that perform free-running operation. When the clock
generated in channel 10 (described below) is selected, these counters can be cleared at the count
specified in channel 10. Each counter can generate an interrupt request when it overflows.
The eight general registers (GR1A to GR1H) can be used as input capture or output compare
registers using the corresponding external signal I/O pin (TIO1A to TIO1H). When used for input
capture, the free-running counter (TCNT1A) value is captured by means of input from the
corresponding external signal I/O pin (TIO1A to TIO1H). Rising edge, falling edge, or both edges
can be selected for the input capture signal in the timer I/O control registers (TIOR1A to
TIOR1D). When used for output compare, compare-match with the free-running counter
(TCNT1A) is performed. For the output from the external signal I/O pins by compare-match, 0
output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR1A to
TIOR1D). When used as output compare registers, a compare-match can be used as a one-shot
pulse start/terminate trigger by setting the channel 8 timer connection register (TCNR) and one-
shot pulse terminate register (OTR), and using these in combination with the down-counters
(DCNT8A to DCNT8H). Start/terminate trigger selection is performed by means of the trigger
mode register (TRGMDR).
The output compare register (OCR1) can be used as a one-shot pulse offset function, in the same
way as the general registers, in combination with channel 8 down-counters DCNT8A to DCNT8H.
An interrupt can be requested on the occurrence of the respective input capture or compare-match.
In addition, channel 1 has a 16-bit dedicated input capture register (OSBR1). The channel 0 TI0A
input pin can also be used as the OSBR1 trigger input, enabling use of a twin-capture function.
Channel 2: Channel 2 has two 16-bit free-running counters (TCNT2A and TCNT2B), eight 16-bit
general registers (GR2A to GR2H), and eight 16-bit output compare registers (OCR2A to
OCR2H).
TCNT2A and TCNT2B are up-counters that perform free-running operation. When the clock
generated in channel 10 (described below) is selected, these counters can be cleared at the count
specified in channel 10. Each counter can generate an interrupt request when it overflows.
The eight general registers (GR2A to GR2H) can be used as input capture or output compare
registers using the corresponding external signal I/O pin (TIO2A to TIO2H). When used for input
capture, the free-running counter (TCNT2A) value is captured by means of input from the
corresponding external signal I/O pin (TIO2A to TIO2H). Rising edge, falling edge, or both edges
can be selected for the input capture signal in the timer I/O control registers (TIOR2A to
TIOR2D). When used for output compare, compare-match with the free-running counter
(TCNT2A) is performed. For the output from the external signal I/O pins by compare-match, 0
output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR2A to
Rev.2.0, 07/03, page 353 of 960