SH7055S Datasheet, PDF (883/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 23 RAM
23.1 Overview
The SH7055SF has 32 kbytes of on-chip RAM. The on-chip RAM is linked to the CPU, direct
memory access controller (DMAC), and advanced user debugger (AUD) with a 32-bit data bus
(figure 23.1).
The CPU, DMAC, and AUD can access data in the on-chip RAM in 8, 16, or 32 bit widths. On-
chip RAM data can always be accessed in one state, making the RAM ideal for use as a program
area, stack area, or data area, which require high-speed access. The contents of the on-chip RAM
are held in both the sleep and software standby modes. When the RAME bit (see below) is cleared
to 0, the on-chip RAM contents are also held in hardware standby mode.
The on-chip RAM is allocated to addresses H'FFFF6000 to H'FFFFDFFF.
SH7055SF
8
bits
H'FFFF6000
H'FFFF6004
Internal data bus (32 bits)
8
8
bits
bits
H'FFFF6001
H'FFFF6005
H'FFFF6002
H'FFFF6006
8
bits
H'FFFF6003
H'FFFF6007
On-chip RAM
H'FFFFDFFC H'FFFFDFFD H'FFFFDFFE H'FFFFDFFF
Figure 23.1 Block Diagram of RAM
Rev.2.0, 07/03, page 845 of 960