SH7055S Datasheet, PDF (552/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

15.5 Usage Notes
Sections 15.5.1 through 15.5.9 provide information concerning use of the SCI.
15.5.1 TDR Write and TDRE Flag
The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data
from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can
be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is
0, however, the old data stored in TDR will be lost because the data has not yet been transferred to
TSR. Before writing transmit data to TDR, be sure to check that TDRE is set to 1.
15.5.2 Simultaneous Multiple Receive Errors
Table 15.13 indicates the state of the SSR status flags when multiple receive errors occur
simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to RDR, so
receive data is lost.
Table 15.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags
Receive Error Status
RDRF
ORER FER PER
Overrun error
1
1
0
0
Framing error
0
0
1
0
Parity error
0
0
0
1
Overrun error + framing error
1
1
1
0
Overrun error + parity error
1
1
0
1
Framing error + parity error
0
0
1
1
Overrun error + framing error + parity 1
error
1
1
1
Notes: O: Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
Receive Data Transfer
RSR → RDR
X
O
O
X
X
O
X
Rev.2.0, 07/03, page 514 of 960