SH7055S Datasheet, PDF (201/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
—
SM1 SM0
—
0
0
0
0
R
R/W R/W
R
10
9
8
—
DM1 DM0
0
0
0
R
R/W R/W
Bit: 7
6
5
4
3
2
1
0
—
—
TS1
TS0
TM
IE
TE
DE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R/W
R/W
R/W
R/W R/(W)*¹ R/W
Notes: *1. TE bit: Allows only a 0 write after reading 1.
*2. The DI and RO bits may be absent, depending on the channel.
• Bits 31–29, 27–25, 23–21, 15, 14, 11, 10, 7, 6—Reserved: These bits are always read as 0, and
should only be written with 0.
• Bit 28—Direct/Indirect Select (DI): Specifies either direct address mode operation or indirect
address mode operation for the channel 3 source address. This bit is valid only in CHCR3. It
always reads 0 in CHCR0–CHCR2, and should always be written with 0.
Bit 28: DI
0
1
Description
Direct access mode operation for channel 3
Indirect access mode operation for channel 3
(Initial value)
• Bit 24—Source Address Reload (RO): Selects whether to reload the source address initial
value during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 in
CHCR0, CHCR1, and CHCR3, and should always be written with 0.
Bit 24: RO
0
1
Description
Does not reload source address
Reloads source address
(Initial value)
Rev.2.0, 07/03, page 163 of 960