SH7055S Datasheet, PDF (603/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

When the mailbox number priority method is selected, if a number of messages are designated
as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-
high mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is then
carried out for the messages in the transmit buffer, and message transmission is performed
when the bus is acquired.
2. Message transmission completion and interrupt
When a message is transmitted normally using the above procedure, the corresponding
acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) and
transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) are automatically
initialized. If the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask
register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register
(IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU.
3. Message transmission cancellation
Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait
message. A transmit wait message is canceled by setting the bit for the corresponding mailbox
(TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is
executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is
set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested.
If the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register
(MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are
set to the interrupt enable value at this time, an interrupt can be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
a. During internal arbitration or CAN bus arbitration
b. During data frame or remote frame transmission
Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure
16.10 shows a flowchart of transmit message cancellation.
4. Message retransmission
If transmission of a transmit message is aborted in the following cases, the message is
retransmitted automatically:
a. CAN bus arbitration failure (failure to acquire the bus)
b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error)
Rev.2.0, 07/03, page 565 of 960