SH7055S Datasheet, PDF (28/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2.6 Timer Interrupt Enable Registers (TIER) ............................................................ 278
11.2.7 Interval Interrupt Request Registers (ITVRR) ..................................................... 300
11.2.8 Trigger Mode Register (TRGMDR) .................................................................... 305
11.2.9 Timer Mode Register (TMDR) ............................................................................ 305
11.2.10 PWM Mode Register (PMDR)............................................................................. 307
11.2.11 Down-Count Start Register (DSTR) .................................................................... 309
11.2.12 Timer Connection Register (TCNR).................................................................... 315
11.2.13 One-Shot Pulse Terminate Register (OTR) ......................................................... 320
11.2.14 Reload Enable Register (RLDENR) .................................................................... 324
11.2.15 Free-Running Counters (TCNT).......................................................................... 325
11.2.16 Down-Counters (DCNT) ..................................................................................... 327
11.2.17 Event Counters (ECNT)...................................................................................... 329
11.2.18 Output Compare Registers (OCR) ....................................................................... 329
11.2.19 Input Capture Registers (ICR) ............................................................................. 330
11.2.20 General Registers (GR)........................................................................................ 331
11.2.21 Offset Base Registers (OSBR) ............................................................................. 334
11.2.22 Cycle Registers (CYLR) ...................................................................................... 334
11.2.23 Buffer Registers (BFR) ........................................................................................ 335
11.2.24 Duty Registers (DTR) .......................................................................................... 336
11.2.25 Reload Register (RLDR)...................................................................................... 337
11.2.26 Channel 10 Registers ........................................................................................... 337
11.3 Operation .......................................................................................................................... 352
11.3.1 Overview.............................................................................................................. 352
11.3.2 Free-Running Counter Operation and Cyclic Counter Operation........................ 359
11.3.3 Compare-Match Function .................................................................................... 360
11.3.4 Input Capture Function ........................................................................................ 361
11.3.5 One-Shot Pulse Function ..................................................................................... 362
11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function ............................. 363
11.3.7 Interval Timer Operation ..................................................................................... 364
11.3.8 Twin-Capture Function........................................................................................ 365
11.3.9 PWM Timer Function .......................................................................................... 366
11.3.10 Channel 3 to 5 PWM Function ............................................................................ 368
11.3.11 Event Count Function and Event Cycle Measurement ........................................ 369
11.3.12 Channel 10 Functions .......................................................................................... 371
11.4 Interrupts........................................................................................................................... 379
11.4.1 Status Flag Setting Timing................................................................................... 379
11.4.2 Status Flag Clearing ............................................................................................. 384
11.5 CPU Interface.................................................................................................................... 386
11.5.1 Registers Requiring 32-Bit Access ...................................................................... 386
11.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access........................................... 388
11.5.3 Registers Requiring 16-Bit Access ...................................................................... 389
11.5.4 8-Bit or 16-Bit Accessible Registers.................................................................... 390
11.5.5 Registers Requiring 8-Bit Access ........................................................................ 391
Rev.2.0, 07/03, page xxviii of xxxviii