SH7055S Datasheet, PDF (651/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

17.4.5 A/D Converter Activation by ATU-II
The A/D0, A/D1, and A/D2 converter modules can be activated by an A/D conversion request
from the ATU-II’s channel 0 interval timer.
To activate the A/D converter by means of the ATU-II, set the TRGE bit to 1 in the A/D control
register (ADCR) and clear the EXTRG bit to 0 in the A/D trigger register (ADTRGR). When an
ATU-II channel 0 interval timer A/D conversion request is generated after these settings have
been made, the ADST bit set to 1. The timing from setting of the ADST bit until the start of A/D
conversion is the same as when 1 is written into the ADST bit by software.
17.4.6 ADEND Output Pin
When channel 31 is used in scan mode, the conversion timing can be monitored with the ADEND
output pin.
After the channel 31 analog voltage has been latched in scan mode, and conversion has started, the
ADEND pin goes high. The ADEND pin subsequently goes low when channel 31 conversion
ends.
ADEND
State of channel 28
(AN28)
Idle
A/D
conversion
Idle
State of channel 29
(AN29)
Idle
A/D
conversion
Idle
State of channel 30
(AN30)
Idle
A/D
conversion
A/D
conversion
Idle
A/D
conversion
Idle
State of channel 31 _A/D
(AN31) conversion
Idle
A/D
conversion
Idle
Figure 17.8 ADEND Output Timing
Rev.2.0, 07/03, page 613 of 960