SH7055S Datasheet, PDF (252/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Block Diagram of Channel 2: Figure 11.4 shows a block diagram of ATU-II channel 2.
STR2A/1B, 2B
Prescaler 1
TCLKA
TCLKB
TI10 (AGCKM)
TI10 multiplication (AGCK)
TIO2A
TIO2B
TIO2C
TIO2D
TIO2E
TIO2F
TIO2G
TIO2H
Clock selection
logic
GR2A
GR2B
GR2C
GR2D
GR2E
GR2F
GR2G
GR2H
OSBR2
TCNT2A
OCR2A
OCR2B
OCR2C
OCR2D
OCR2E
OCR2F
OCR2G
OCR2H
TCNT2B
TIOR2A
TIOR2B
TIOR2C
TIOR2D
TCR2A
TCR2B
TSR2A
TSR2B
TIER2A
TIER2B
Control
logic
I/O control
Internal data bus and address bus
Compa-
rator
TI0A
(couter clear trigger from CH0)
TRG2A
(counter clear trigger
from CH10)
TRG2B
(counter clear trigger
from CH10)
One-shot start
trigger (CH8)
One-shot terminate
trigger (CH8)
Overflow interrupt × 1
Input capture/output
compare interrupts × 8
Figure 11.4 Block Diagram of Channel 2
Rev.2.0, 07/03, page 214 of 960