SH7055S Datasheet, PDF (192/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

9.5 Bus Arbitration
The SH7058 has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device. It also has three internal bus masters, the CPU,
DMAC, and AUD. The priority ranking for determining bus right transfer between these bus
masters is:
Bus right request from external device > AUD > DMAC > CPU
Therefore, an external device that generates a bus request is given priority even if the request is
made during a DMAC burst transfer.
The AUD does not acquire the bus during DMAC burst transfer, but at the end of the transfer.
When the CPU has possession of the bus, the AUD has higher priority than the DMAC for bus
acquisition.
A bus request by an external device should be input at the BREQ pin. The signal indicating that
the bus has been released is output from the BACK pin.
Figure 9.9 shows the bus right release procedure.
SH7055SF
accepted
= Low
External device
Bus right request
Strobe pin:
high-level output
Address, data,
strobe pin:
high impedance
Bus right release
response
= Low
confirmation
Bus right release status
Bus right acquisition
Figure 9.9 Bus Right Release Procedure
Rev.2.0, 07/03, page 154 of 960