SH7055S Datasheet, PDF (453/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow
occurs in the T2 state of a down-counter start register (DSTR) “1” write cycle by the CPU,
clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1.
The timing in this case is shown in figure 11.73.
STR write cycle
T1
T2
Pø
Address
Internal write signal
DSTR address
1 written
to DSTR
DCNT 0001
0000
0000
Underflow signal
Down-count start
register
Figure 11.73 Contention between DSTR Bit Setting by CPU and Clearing by Underflow
Rev.2.0, 07/03, page 415 of 960