SH7055S Datasheet, PDF (532/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

1
Serial
data
Start
bit
0 D0
Parity Stop Start
Data bit bit bit
D1 D7 0/1 1 0 D0
Parity Stop
Data bit bit
D1 D7 0/1 1
1
Idling
(marking)
TDRF
FER
RXI interrupt request
1 frame
RXI interrupt
handler reads
data in RDR and
clears RDRF to 0.
Framing error
generates
ERI interrupt
request.
Figure 15.9 SCI Receive Operation
(Example: 8-Bit Data with Parity and One Stop Bit)
15.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line for sending and receiving data. The processors communicate in the
asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which
it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting
processor sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 15.10 shows an example of communication among processors using the multiprocessor
format.
Rev.2.0, 07/03, page 494 of 960