SH7055S Datasheet, PDF (553/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

15.5.3 Break Detection and Processing
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the
parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so
if the FER bit is cleared to 0, it will be set to 1 again.
15.5.4 Sending a Break Signal
The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O
port data register (DR) and pin function controller (PFC) control register (CR). These conditions
allow break signals to be sent. The DR value is substituted for the marking status until the PFC is
set. Consequently, the output port is set to initially output a 1. To send a break in serial
transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC.
When TE is cleared to 0, the transmission section is initialized regardless of the present
transmission status.
15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only)
When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting
even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit.
Note that clearing RE to 0 does not clear the receive error flags.
15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer
rate. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it
samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse
(figure 15.25).
Rev.2.0, 07/03, page 515 of 960