SH7055S Datasheet, PDF (94/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 2.18 Floating-Point Instructions
Instruction
Instruction Code
Operation
Execu-
tion
Cycles T Bit
FABS FRn
1111nnnn01011101 |FRn| → FRn
1
—
FADD FRm,FRn
1111nnnnmmmm0000 FRn + FRm → FRn
1
—
FCMP/EQ FRm,FRn
1111nnnnmmmm0100 (FRn = FRm)? 1:0 → T 1
Comparison
result
FCMP/GT FRm,FRn
1111nnnnmmmm0101 (FRn > FRm)? 1:0 → T 1
Comparison
result
FDIV FRm,FRn
1111nnnnmmmm0011 FRn/FRm → FRn
13
—
FLDI0 FRn
1111nnnn10001101 0x00000000 → FRn 1
—
FLDI1 FRn
1111nnnn10011101 0x3F800000 → FRn 1
—
FLDS FRm,FPUL
1111mmmm00011101 FRm → FPUL
1
—
FLOAT FPUL,FRn
1111nnnn00101101 (float) FPUL → FRn 1
—
FMAC FR0,FRm,FRn 1111nnnnmmmm1110 FR0 × FRm + FRn → 1
—
FRn
FMOV FRm, FRn
1111nnnnmmmm1100 FRm → FRn
1
—
FMOV.S @(R0,Rm),FRn 1111nnnnmmmm0110 (R0 + Rm) → FRn
1
—
FMOV.S @Rm+,FRn
1111nnnnmmmm1001 (Rm) → FRn, Rm+ = 4 1
—
FMOV.S @Rm,FRn
1111nnnnmmmm1000 (Rm) → FRn
1
—
FMOV.S FRm,@(R0,Rn) 1111nnnnmmmm0111 FRm → (R0 + Rn)
1
—
FMOV.S FRm,@-Rn
1111nnnnmmmm1011 Rn– = 4, FRm → (Rn) 1
—
FMOV.S FRm,@Rn
1111nnnnmmmm1010 FRm → (Rn)
1
—
FMUL FRm,FRn
1111nnnnmmmm0010 FRn × FRm → FRn
1
—
FNEG FRn
1111nnnn01001101 –FRn → FRn
1
—
FSTS FPUL,FRn
1111nnnn00001101 FPUL → FRn
1
—
FSUB FRm,FRn
1111nnnnmmmm0001 FRn – FRm → FRn
1
—
FTRC FRm,FPUL
1111mmmm00111101 (long) FRm → FPUL 1
—
Rev.2.0, 07/03, page 56 of 960