SH7055S Datasheet, PDF (367/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2.17 Event Counters (ECNT)
The event counters (ECNT) are 8-bit up-counters. The ATU-II has six ECNT counters in channel
9.
Channel
9
Abbreviation
ECNT9A, ECNT9B,
ECNT9C, ECNT9D,
ECNT9E, ECNT9F
Function
8-bit event counters
The ECNT counters are 8-bit readable/writable registers that count on detection of an input signal
from input pins TI9A to TI9F. Rising edge, falling edge, or both rising and falling edges can be
selected for edge detection.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
When a compare-match with GR9 corresponding to an ECNT9x counter occurs, the compare-
match flag (CMF9) in the timer status register (TSR9) is set to 1. When a compare-match with GR
occurs, the ECNT9x counter is cleared automatically.
The ECNT9x counters can only be accessed by a byte read or write.
The ECNT9x counters are initialized to H'00 by a power-on reset, and in hardware standby mode
and software standby mode.
11.2.18 Output Compare Registers (OCR)
The output compare registers (OCR) are 16-bit registers. The ATU-II has nine OCR registers: one
in channel 1 and eight in channel 2. For details of the channel 10 free-running counters, see
section 11.2.26, Channel 10 Registers.
Channel
1
2
Abbreviation
OCR1
OCR2A, OCR2B,
OCR2C, OCR2D,
OCR2E, OCR2F,
OCR2G, OCR2H
Function
Output compare registers
Rev.2.0, 07/03, page 329 of 960