SH7055S Datasheet, PDF (432/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Sample Setup Procedure for Channel 0 Input Capture Triggered by Channel 10 Compare-
Match: An example of the setup procedure for compare-match signal transmission is shown in
figure 11.55.
1. Set the timing for compare-match generation in the channel 10 output compare register
(OCR10B).
2. Set the TRG0DEN bit to 1 in the channel 10 timer control register (TCR10).
3. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 10 free-
running counter (TCNT10B). On compare-match between TCNT10 and OCR10B, the
compare-match signal is transmitted to channel 0 as the channel 0 ICR0D input capture signal.
Start
Set compare-match ¹
Set TCR10
2
Start counter
3
Signal transmission
Figure 11.55 Sample Setup Procedure for Compare-Match Signal Transmission
Rev.2.0, 07/03, page 394 of 960