SH7055S Datasheet, PDF (102/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

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19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Cause field Enable field Flag field
DN CE CV CZ CO CU CI EV EZ EO EU EI FV FZ FO FU FI RM
DN: Denormalized bit
In the SH7055SF this bit is always set to 1, and the source or destination operand
of a denormalized number is 0. This bit cannot be modified even by an LDS
instruction.
CV: Invalid operation cause bit
When 1: Indicates that an invalid operation exception occurred during execution
of the current instruction.
When 0: Indicates that an invalid operation exception has not occurred.
CZ: Division-by-zero cause bit
When 1: Indicates that a division-by-zero exception occurred during execution
of the current instruction.
When 0: Indicates that a division-by-zero exception has not occurred.
EV: Invalid operation exception enable
When 1: Enables invalid operation exception generation.
When 0: An invalid operation exception is not generated, and a qNAN is returned
as the result.
EZ: Division-by-zero exception enable
When 1: Enables exception generation due to division-by-zero during execution
of the current instruction.
When 0: A division-by-zero exception is not generated, and infinity with the sign
(+ or –) of the current expression is returned as the result.
FV: Invalid operation exception flag bit
When 1: Indicates that an invalid operation exception occurred during instruction
execution.
When 0: Indicates that an invalid operation exception has not occurred.
FZ: Division-by-zero exception flag bit
When 1: Indicates that a division-by-zero exception occurred during instruction
execution.
When 0: Indicates that a division-by-zero exception has not occurred.
RM: Rounding bit.
In the SH7055SF, the value of these bits is always 01, meaning that rounding to
zero (RZ mode) is being used. These bits cannot be modified even by an LDS
instruction.
In the SH7055SF, the cause field EOUI bits (CE, CO, CU, and CI), enable field OUI bits
(EO, EU, and EI), and flag field OUI bits (FO, FU, and FI), and the reserved area, are
preset to 0, and cannot be modified even by using an LDS instruction.
Figure 3.2 Floating-Point Status/Control Register
Rev.2.0, 07/03, page 64 of 960