SH7055S Datasheet, PDF (136/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

7.2 Interrupt Sources
There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral
modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and
16 the highest). Giving an interrupt a priority level of 0 masks it.
7.2.1 NMI Interrupts
The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by
edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either
the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits
(I3–I0) in the status register (SR) to level 15.
7.2.2 User Break Interrupt
A user break interrupt has a priority of level 15, and occurs when the break condition set in the
user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are
held until accepted. User break interrupt exception processing sets the interrupt mask level bits
(I3–I0) in the status register (SR) to level 15. For more information about the user break interrupt,
see section 8, User Break Controller (UBC).
7.2.3 H-UDI Interrupt
A serial debug interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-UDI
interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are held
until accepted. H-UDI exception processing sets the interrupt mask level bits (I3-I0) in the status
register (SR) to level 15. For more information about the H-UDI interrupt, see section 18, High-
Performance User Debug Interface (H-UDI).
7.2.4 IRQ Interrupts
IRQ interrupts are requested by input from pins IRQ0–IRQ7. Set the IRQ sense select bits
(IRQ0S–IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge
detection for each pin. The priority level can be set from 0 to 15 for each pin using interrupt
priority registers A and B (IPRA–IPRB).
When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC
during the period the IRQ pin is low. Interrupt request signals are not sent to the INTC when the
IRQ pin becomes high. Interrupt request levels can be confirmed by reading the IRQ flags
(IRQ0F–IRQ7F) of the IRQ status register (ISR).
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