SH7055S Datasheet, PDF (302/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 12—Input Capture/Compare-Match Flag 5C (IMF5C): Status flag that indicates GR5C
input capture or compare-match. The flag is not set in PWM mode.
Bit 12: IMF5C
0
1
Description
[Clearing condition]
(Initial value)
When IMF5C is read while set to 1, then 0 is written to IMF5C
[Setting conditions]
• When the TCNT5 value is transferred to GR5C by an input capture signal
while GR5C is functioning as an input capture register
• When TCNT5 = GR5C while GR5C is functioning as an output compare
register
• Bit 11—Input Capture/Compare-Match Flag 5B (IMF5B): Status flag that indicates GR5B
input capture or compare-match. The flag is not set in PWM mode.
Bit 11: IMF5B
0
1
Description
[Clearing condition]
(Initial value)
When IMF5B is read while set to 1, then 0 is written to IMF5B
[Setting conditions]
• When the TCNT5 value is transferred to GR5B by an input capture signal
while GR5B is functioning as an input capture register
• When TCNT5 = GR5B while GR5B is functioning as an output compare
register
• Bit 10—Input Capture/Compare-Match Flag 5A (IMF5A): Status flag that indicates GR5A
input capture or compare-match. The flag is not set in PWM mode.
Bit 10: IMF5A
0
1
Description
[Clearing condition]
(Initial value)
When IMF5A is read while set to 1, then 0 is written to IMF5A
[Setting conditions]
• When the TCNT5 value is transferred to GR5A by an input capture signal
while GR5A is functioning as an input capture register
• When TCNT5 = GR5A while GR5A is functioning as an output compare
register
Rev.2.0, 07/03, page 264 of 960