SH7055S Datasheet, PDF (120/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 6.3 Exception Processing Vector Table (cont)
Exception Sources
Vector
Numbers
Vector Table Address†Offset
Slot illegal instruction
6
H'00000018–H'0000001B
(Reserved by system)
7
H'0000001C–H'0000001F
8
H'00000020–H'00000023
CPU address error
9
H'00000024–H'00000027
DMAC address error
10
H'00000028–H'0000002B
Interrupts
NMI
11
H'0000002C–H'0000002F
User break
12
H'00000030–H'00000033
FPU exception
13
H'00000034–H'00000037
H-UDI
14
H'00000038–H'0000003B
(Reserved by system)
16
H'0000003C–H'00000043
:
:
31
H'0000007C–H'0000007F
Trap instruction (user vector)
32
H'00000080–H'00000083
:
:
63
H'000000FC–H'000000FF
Interrupts
IRQ0
64
H'00000100–H'00000103
IRQ1
65
H'00000104–H'00000107
IRQ2
66
H'00000108–H'0000010B
IRQ3
67
H'0000010C–H'0000010F
IRQ4
68
H'00000110–H'00000113
IRQ5
69
H'00000114–H'00000117
IRQ6
70
H'00000118–H'0000011B
IRQ7
71
H'0000011C–H'0000011F
On-chip peripheral module*
72
H'00000120–H'00000124
:
:
255
H'000003FC–H'000003FF
Note: * The vector numbers and vector table address offsets for each on-chip peripheral module
interrupt are given in table 7.3, Interrupt Exception Processing Vectors and Priorities, in
section 7, Interrupt Controller (INTC).
Rev.2.0, 07/03, page 82 of 960