SH7055S Datasheet, PDF (362/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2.14 Reload Enable Register (RLDENR)
The reload enable register (RLDENR) is an 8-bit register. The ATU-II has one RLDENR register
in channel 8.
Bit: 7
6
5
4
3
2
1
0
RLDEN —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
RLDENR is an 8-bit readable/writable register that enables or disables loading of the reload
register8 (RLDR8) value into the down-counters (DCNT8I to DCNT8P). Loading is performed on
generation of a channel 2 compare-match signal one-shot pulse start trigger. Reloading is not
performed if there is no linkage with channel 2 (one-shot pulse function), or while the down-
counter (DCNT8I to DCNT8P) is running.
RLDENR is initialized to H'00 by a power-on reset and in hardware standby mode and software
standby mode.
• Bit 7—Reload Enable (RLDEN): Enables or disables loading of the RLDR value into DCNT8I
to DCNT8P.
Bit 7: RLDEN
0
1
Description
Loading of reload register value into down-counters is disabled (Initial value)
Loading of reload register value into down-counters is enabled
• Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev.2.0, 07/03, page 324 of 960