SH7055S Datasheet, PDF (369/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Input Capture Registers 0AH, 0AL to 0DH, 0DL (ICR0AH, ICR0AL to ICR0DH, ICR0DL)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
The ICR registers are 32-bit read-only registers used exclusively for input capture.
These dedicated input capture registers store the TCNT0 value on detection of an input capture
signal from an external source. The corresponding TSR0 bit is set to 1 at this time. The input
capture signal edge to be detected is specified by timer I/O control register TIOR0. By setting the
TRG0DEN bit in TCR10, ICR0DH and ICR0DL can also be used for input capture in a compare
match between TCNT10B and OCR10B.
The ICR registers can only be accessed by a longword read. Word reads cannot be used.
The ICR registers are initialized to H'00000000 by a power-on reset, and in hardware standby
mode and software standby mode.
11.2.20 General Registers (GR)
The general registers (GR) are 16-bit registers. The ATU-II has 36 general registers: eight each in
channels 1 and 2, four each in channels 3 to 5, six in channel 9, and two in channel 11. For details
of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers.
Channel
1
2
3
4
5
9
11
Abbreviation
GR1A–GR1H
GR2A–GR2H
GR3A–GR3D
GR4A–GR4D
GR5A–GR5D
GR9A–GR9F
GR11A, GR11B
Function
Dual-purpose input capture and output compare registers
Dedicated output compare registers
Dual-purpose input capture and output compare registers
Rev.2.0, 07/03, page 331 of 960