SH7055S Datasheet, PDF (220/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

10.3.8 Bus Mode and Channel Priorities
If, for example, a transfer request is issued for channel 0 while transfer is in progress on lower-
priority channel 1 in burst mode, transfer is started immediately on channel 0.
In this case, if channel 0 is set to burst mode, channel 1 transfer is continued after completion of
all transfers on channel 0. If channel 0 is set to cycle-steal mode, channel 1 transfer is continued
only if a channel 0 transfer request has not been issued; if a transfer request is issued, channel 0
transfer is started immediately.
10.3.9 Source Address Reload Function
Channel 2 has a source address reload function. This returns to the first value set in the source
address register (SAR2) every four transfers by setting the RO bit of CHCR2 to 1. Figure 10.10
illustrates this operation. Figure 10.11 is a timing chart for use of channel 2 only with the
following transfer conditions set: burst mode, auto-request, 16-bit transfer data size, SAR2
incremented, DAR2 fixed, reload function on.
DMAC
DMAC control block
Transfer
request
Reload control
4th count
RO bit = 1
CHCR2
Count signal
DMATCR2
Reload signal
Reload
signal
SAR2
(initial value)
SAR2
Figure 10.10 Source Address Reload Function
Rev.2.0, 07/03, page 182 of 960