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SH7055S Datasheet, PDF (473/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series | |||
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⢠Bit 5âTimer Enable (TME): Enables or disables the timer.
Bit 5: TME
0
1
Description
Timer disabled: TCNT is initialized to H'00 and count-up stops
(Initial value)
Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is
generated when TCNT overflows.
⢠Bits 4 and 3âReserved: These bits always read 1. The write value should always be 1.
⢠Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources for input to TCNT. The clock signals are obtained by dividing the frequency of the
system clock (Ï).
Description
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source
Overflow Interval*
(Ï = 40 MHz)
0
0
0
Ï/2 (Initial value) 12.8 µs
0
0
1
Ï/64
409.6 µs
0
1
0
Ï/128
0.8 ms
0
1
1
Ï/256
1.6 ms
1
0
0
Ï/512
3.3 ms
1
0
1
Ï/1024
6.6 ms
1
1
0
Ï/4096
26.2 ms
1
1
1
Ï/8192
52.4 ms
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an
overflow occurs.
Rev.2.0, 07/03, page 435 of 960
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