SH7055S Datasheet, PDF (583/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to
bus operation in sleep mode.
Bit 4: IMR12
0
1
Description
Bus operation interrupt request (OVR) to CPU by IRR12 enabled
Bus operation interrupt request (OVR) to CPU by IRR12 disabled
(Initial value)
• Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite
interrupt requests.
Bit 1: IMR9
0
1
Description
Unread message overwrite interrupt request (OVR) to CPU by IRR9 enabled
Unread message overwrite interrupt request (OVR) to CPU by IRR9
disabled
(Initial value)
• Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt
requests.
Bit 0: IMR8
0
1
Description
Mailbox empty interrupt request (SLE) to CPU by IRR8 enabled
Mailbox empty interrupt request (SLE) to CPU by IRR8 disabled
(Initial value)
16.2.14 Receive Error Counter (REC)
The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating
the number of receive message errors on the CAN bus. The count value is stipulated in the CAN
protocol. This register cannot be modified.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Rev.2.0, 07/03, page 545 of 960