SH7055S Datasheet, PDF (154/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

7.5 Interrupt Response Time
Table 7.5 indicates the interrupt response time, which is the time from the occurrence of an
interrupt request until the interrupt exception processing starts and fetching of the first instruction
of the interrupt service routine begins. Figure 7.4 shows an example of pipeline operation when an
IRQ interrupt is accepted.
Table 7.5 Interrupt Response Time
Number of States
Item
NMI, Peripheral
Module
IRQ
DMAC activation judgment 0 or 1
0
Compare identified inter- 2
3
rupt priority with SR mask
level
Wait for completion of
X (≥ 0)
sequence currently being
executed by CPU
Time from start of interrupt 5 + m1 + m2 + m3
exception processing until
fetch of first instruction of
exception service routine
starts
Notes
1 state required for interrupt
signals for which DMAC
activation is possible
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Performs the PC and SR
saves and vector address
fetch.
Interrupt
response
time
Total:
(7 or 8) + m1 +
m2 + m3 + X
Minimum: 10
8 + m1 + m2 +
m3 + X
11
0.25 to 0.28 µs at 40 MHz
Maximum: 12 + 2 (m1 + m2 + 12 + 2 (m1 + m2 + 0.48 µs at 40 MHz*
m3) + m4
m3) + m4
Note: * When m1 = m2 = m3 = m4 = 1
m1–m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Rev.2.0, 07/03, page 116 of 960