SH7055S Datasheet, PDF (323/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 5—Input Capture/Compare-Match Interrupt Enable 2F (IME2F): Enables or disables
interrupt requests by IMF2F in TSR2A when IMF2F is set to 1.
Bit 5: IME2F
0
1
Description
IMI2F interrupt requested by IMF2F is disabled
IMI2F interrupt requested by IMF2F is enabled
(Initial value)
• Bit 4—Input Capture/Compare-Match Interrupt Enable 2E (IME2E): Enables or disables
interrupt requests by IMF2E in TSR2A when IMF2E is set to 1.
Bit 4: IME2E
0
1
Description
IMI2E interrupt requested by IMF2E is disabled
IMI2E interrupt requested by IMF2E is enabled
(Initial value)
• Bit 3—Input Capture/Compare-Match Interrupt Enable 2D (IME2D): Enables or disables
interrupt requests by IMF2D in TSR2A when IMF2D is set to 1.
Bit 3: IME2D
0
1
Description
IMI2D interrupt requested by IMF2D is disabled
IMI2D interrupt requested by IMF2D is enabled
(Initial value)
• Bit 2—Input Capture/Compare-Match Interrupt Enable 2C (IME2C): Enables or disables
interrupt requests by IMF2C in TSR2A when IMF2C is set to 1.
Bit 2: IME2C
0
1
Description
IMI2C interrupt requested by IMF2C is disabled
IMI2C interrupt requested by IMF2C is enabled
(Initial value)
• Bit 1—Input Capture/Compare-Match Interrupt Enable 2B (IME2B): Enables or disables
interrupt requests by IMF2B in TSR2A when IMF2B is set to 1.
Bit 1: IME2B
0
1
Description
IMI2B interrupt requested by IMF2B is disabled
IMI2B interrupt requested by IMF2B is enabled
(Initial value)
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