SH7055S Datasheet, PDF (298/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 1—Input Capture/Compare-Match Flag 2B (IMF2B): Status flag that indicates GR2B input
capture or compare-match.
Bit 1: IMF2B
0
1
Description
[Clearing condition]
(Initial value)
When IMF2B is read while set to 1, then 0 is written to IMF2B
[Setting conditions]
• When the TCNT2A value is transferred to GR2B by an input capture
signal while GR2B is functioning as an input capture register
• When TCNT2A = GR2B while GR2B is functioning as an output compare
register
• Bit 0—Input Capture/Compare-Match Flag 2A (IMF2A): Status flag that indicates GR2A
input capture or compare-match.
Bit 0: IMF2A
0
1
Description
[Clearing condition]
(Initial value)
When IMF2A is read while set to 1, then 0 is written to IMF2A
[Setting conditions]
• When the TCNT2A value is transferred to GR2A by an input capture
signal while GR2A is functioning as an input capture register
• When TCNT2A = GR2A while GR2A is functioning as an output compare
register
TSR2B: TSR2B indicates the status of channel 2 compare-match and overflow.
Bit: 15
14
13
12
11
10
9
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
OVF2B
0
R/(W)*
Bit: 7
6
5
4
3
2
1
0
CMF2H CMF2G CMF2F CMF2E CMF2D CMF2C CMF2B CMF2A
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag.
Rev.2.0, 07/03, page 260 of 960