SH7055S Datasheet, PDF (937/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

26.3.11 H-UDI Timing
Table 26.16 shows H-UDI timing.
Table 26.16 H-UDI Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol Min
Max
Unit Figures
TCK clock cycle
TCK clock high-level width
TCK clock low-level width
TRST pulse width
TRST setup time
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TDO delay time
t_tcyc
t_TCKH
t
TCKL
t
TRSW
t
TRSS
t_TMSS
t_TMSH
t_TDIS
t
TDIH
t
TDOD
4
—
t_tcyc
Figure 26.21
0.4
0.6
t_tcyc
0.4
0.6
t
tcyc
20
—
t
Figure 26.22
cyc
30
—
ns
30
—
ns
Figure 26.23
10
—
ns
30
—
ns
10
—
ns
—
30
ns
[Operating precautions]
The H-UDI pins constitute a circuit requiring the voltage of V_CC = 3.3 V ±0.3 V. Comply with the
input and output voltages specified in the DC characteristics, for operation.
TCK
t_TCKH
t_TCKL
V_IH
V_IH
V_IL
t_tcyc
V_IH
V_IL
Table 26.21 H-UDI Clock Timing
Rev.2.0, 07/03, page 899 of 960