SH7055S Datasheet, PDF (198/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 10.1 DMAC Registers (cont)
Channel Name
Abbr.
Initial
R/W Value
Address
Register Access
Size
Size
3
DMA source
SAR3
R/W Undefined H'FFFFECF0 32 bits 16, 32*²
address register 3
DMA destination DAR3
address register 3
R/W Undefined H'FFFFECF4 32 bits 16, 32*²
DMA transfer
count register 3
DMATCR3 R/W Undefined H'FFFFECF8 32 bits 16, 32*³
DMA channel
control register 3
CHCR3
R/W*¹ H'00000000 H'FFFFECFC 32 bits
16, 32*²
Shared DMA operation
register
DMAOR R/W*¹ H'0000
H'FFFFECB0 16 bits 16*⁴
Notes: Word access to a register takes 3 cycles, and longword access 6 cycles.
Do not attempt to access an empty address, as operation canot be guaranteed if this is
done.
*1 Write 0 after reading 1 in bit 1 of CHCR0–CHCR3 and in bits 1 and 2 of DMAOR to
clear flags. No other writes are allowed.
*2 For 16-bit access of SAR0–SAR3, DAR0–DAR3, and CHCR0–CHCR3, the 16-bit value
on the side not accessed is held.
*3 DMATCR has a 24-bit configuration: bits 0–23. Writing to the upper 8 bits (bits 24–31)
is invalid, and these bits always read 0.
*4 Do not use 32-bit access on DMAOR.
10.2 Register Descriptions
10.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a count function, and during a
DMA transfer, they indicate the next source address.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when
performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.
The initial value after a power-on reset and in standby mode is undefined.
Rev.2.0, 07/03, page 160 of 960