SH7055S Datasheet, PDF (413/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Multiplied Clock Correction Function: Channel 10’s three 16-bit correction counters
(TCNT10D, TCNT10E, TCNT10F) and correction counter clear register (TCCLR10) have a
correction function that makes the interval between edges input from TI10 the frequency
multiplication value set in TIOR10.
When AGCK is input, the value in TCNT10D multiplied by the multiplication factor set in
TIOR10 is transferred to TCNT10E. At the same time, TCNT10D is incremented.
TCNT10E counts up on AGCK1. TCNT10E loads TCNT10D on AGCK, and counts up again on
AGCK1. Using the counter correction select bit (CCS) in TIOR10, it is possible to select whether
or not TCNT10E is halted when TCNT10D = TCNT10E.
TCNT10F has the peripheral clock (Pφ) as its input and is constantly compared with TCNT10E.
When the TCNT10F value is smaller than that in TCNT10E, TCNT10F is incremented and
outputs a corrected multiplied clock signal (AGCKM).
When the TCNT10E value exceeds the TCNT10F value (when TCNT10E loads TCNT10D), no
count-up operation is performed. AGCKM is output to the channel 1 to 5 free-running counters
(TCNT1 to TCNT5).
Channel 10 also has a correction counter clear register (TCCLR10). The correction counters
(TCNT10D, TCNT10E, TCNT10F) and channel 1 and 2 free-running counters (TCNT1 and
TCNT2) can be cleared when TCNT10F reaches the value set in TCCLR10.
TCNT10D operation is shown in figure 11.32, TCNT10E operation in figure 11.33, TCNT10F
operation (at startup) in figure 11.34, TCNT10F operation (end of cycle, acceleration,
deceleration) in figure 11.35, and TCNT10F operation (end of cycle, steady-state) in figure 11.36.
Pø
TST10
AGCK
TCNT10D
Clock
TCNT10D
Shifter output
00
0000
01
0020
02
0040
Figure 11.32 TCNT10D Operation
03
0060
Note: In case of multiplication factor of 32
Rev.2.0, 07/03, page 375 of 960