SH7055S Datasheet, PDF (272/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
• Bits 6 to 4—Clock Select B2 to B0 (CKSELB2 to CKSELB0): These bits, relating to counters
DCNT8I to DCNT8P, select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4,
φ'/8, φ'/16, and φ'/32.
Bit 6:
CKSELB2
0
1
Bit 5:
CKSELB1
0
1
0
1
Bit 4:
CKSELB0
0
1
0
1
0
1
0
1
Description
Internal clock φ": counting on φ'
Internal clock φ": counting on φ'/2
Internal clock φ": counting on φ'/4
Internal clock φ": counting on φ'/8
Internal clock φ": counting on φ'/16
Internal clock φ": counting on φ'/32
Setting prohibited
Setting prohibited
(Initial value)
• Bit 3—Reserved: This bit is always read as 0. The write value should always be 0.
• Bits 2 to 0—Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits, relating to counters
DCNT8A to DCNT8H, select clock φ", scaled from the internal clock source, from φ', φ'/2,
φ'/4, φ'/8, φ'/16, and φ'/32.
Bit 2:
CKSELA2
0
1
Bit 1:
CKSELA1
0
1
0
1
Bit 0:
CKSELA0
0
1
0
1
0
1
0
1
Description
Internal clock φ": counting on φ'
Internal clock φ": counting on φ'/2
Internal clock φ": counting on φ'/4
Internal clock φ": counting on φ'/8
Internal clock φ": counting on φ'/16
Internal clock φ": counting on φ'/32
Setting prohibited
Setting prohibited
(Initial value)
Rev.2.0, 07/03, page 234 of 960