SH7055S Datasheet, PDF (291/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Timer Status Registers 1A and 1B (TSR1A, TSR1B)
TSR1A: TSR1A indicates the status of channel 1 input capture, compare-match, and overflow.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVF1A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/(W)*
Bit:
Initial value:
R/W:
7
IMF1H
0
R/(W)*
6
IMF1G
0
R/(W)*
5
IMF1F
0
R/(W)*
4
IMF1E
0
R/(W)*
3
IMF1D
0
R/(W)*
2
IMF1C
0
R/(W)*
1
IMF1B
0
R/(W)*
0
IMF1A
0
R/(W)*
Note: * Only 0 can be written, to clear the flag.
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Flag 1A (OVF1A): Status flag that indicates TCNT1A overflow.
Bit 8: OVF1A
0
1
Description
[Clearing condition]
(Initial value)
When OVF1A is read while set to 1, then 0 is written to OVF1A
[Setting condition]
When the TCNT1A value overflows (from H'FFFF to H'0000)
• Bit 7—Input Capture/Compare-Match Flag 1H (IMF1H): Status flag that indicates GR1H
input capture or compare-match.
Bit 7: IMF1H
0
1
Description
[Clearing condition]
(Initial value)
When IMF1H is read while set to 1, then 0 is written to IMF1H
[Setting conditions]
• When the TCNT1A value is transferred to GR1H by an input capture
signal while GR1H is functioning as an input capture register
• When TCNT1A = GR1H while GR1H is functioning as an output compare
register
Rev.2.0, 07/03, page 253 of 960