SH7055S Datasheet, PDF (657/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

18.1.3 Pin Configuration
Table 18.1 shows the H-UDI pin configuration.
Table 18.1 H-UDI Pins
Name
Test clock
Test mode select
Test data input
Test data output
Test reset
Abbreviation
TCK
TMS
TDI
TDO
TRST
I/O
Input
Input
Input
Output
Input
Function
Test clock input
Test mode select input signal
Serial data input
Serial data output
Test reset input signal
18.1.4 Register Configuration
Table 18.2 shows the H-UDI registers.
Table 18.2 H-UDI Registers
Register
Initial
Abbreviation R/W*¹ Value*²
Address
Access Size
(Bits)
Instruction register SDIR
R
H'F000
H'FFFFF7C0 8/16/32
Status register
SDSR
R/W H'0201
H'FFFFF7C2 8/16/32
Data register H
SDDRH
R/W Undefined H'FFFFF7C4 8/16/32
Data register L
SDDRL
R/W Undefined H'FFFFF7C6 8/16/32
Bypass register
SDBPR
—
—
—
—
Notes: *1 Indicates whether the register can be read and written to by the CPU.
*2 Initial value when the TRST signal is input. Not initialized by a reset (power-on or
manual) or in software standby mode.
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by
serial transfer from the test data input pin (TDI). Data from SDIR, the status register (SDSR), and
SDDR can be output via the test data output pin (TDO). The bypass register (SDBPR) is a one-bit
register that is connected to TDI and TDO in bypass mode. Except for SDBPR, all the registers
can be accessed by the CPU.
Table 18.3 shows the kinds of serial transfer that can be used with each of the H-UDI’s registers.
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