SH7055S Datasheet, PDF (195/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 Direct Memory Access Controller (DMAC)
10.1 Overview
The SH7055SF includes an on-chip four-channel direct memory access controller (DMAC). The
DMAC can be used in place of the CPU to perform high-speed data transfers among external
memories, memory-mapped external devices, and on-chip peripheral modules (except for the
DMAC, BSC, and UBC). Using the DMAC reduces the burden on the CPU and increases the
operating efficiency of the chip as a whole.
10.1.1 Features
The DMAC has the following features:
• Four channels
• 4-Gbyte address space in the architecture
• 8-, 16-, or 32-bit selectable data transfer length
• Maximum of 16 M (6,777,216) transfers
• Address modes
Both the transfer source and transfer destination are accessed by address. There are two
transfer modes: direct address and indirect address.
 Direct address transfer mode: Values set in a DMAC internal register indicate the accessed
address for both the transfer source and transfer destination. Two bus cycles are required
for one data transfer.
 Indirect address transfer mode: The value stored at the location pointed to by the address
set in the DMAC internal transfer source register is used as the address. Operation is
otherwise the same as for direct access. This function can only be set for channel 3. Four
bus cycles are required for one data transfer.
• Channel function: Dual address mode is supported on all channels.
Channel 2 has a source address reload function that reloads the source address every fourth
transfer. Direct address transfer mode or indirect address transfer mode can be specified for
channel 3.
• Reload function
Enables automatic reloading of the value set in the first source address register every fourth
DMA transfer. This function can be executed on channel 2 only.
• Transfer requests
There are two DMAC transfer activation requests, as indicated below.
 Requests from on-chip peripheral modules: Transfer requests from on-chip modules such
as the SCI or A/D. These can be received by all channels.
 Auto-request: The transfer request is generated automatically within the DMAC.
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