SH7055S Datasheet, PDF (617/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.5 Usage Notes
Reset: The HCAN is reset by a power-on reset, and in hardware standby mode and software
standby mode. All the registers are initialized in a reset, but mailboxes (message control
(MCx[x])/message data (MDx[x]) are not. However, after powering on, mailboxes (message
control (MCx[x])/message data (MDx[x]) are initialized, and their values are undefined.
Therefore, mailbox initialization must always be carried out after a power-on reset or a transition
to hardware standby mode or software standby mode. The reset interrupt flag (IRR0) is always set
after a power-on reset or recovery from software standby mode. As this bit cannot be masked in
the interrupt mask register (IMR), if HCAN interrupt enabling is set in the interrupt controller
without clearing the flag, an HCAN interrupt will be initiated immediately. IRR0 should therefore
be cleared during initialization.
HCAN Sleep Mode: The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set
by bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate
sleep mode release. Also note that the reset status bit (GSR3) in the general status register (GSR)
is set in sleep mode.
Port Settings: Port settings must be made with the PFC before the HCAN begins CAN bus
communication.
When using the two HCAN pins in a 2-channel/32-buffer configuration (wired-AND), set the
other two HCAN pin locations as non-HCAN.
DMAC Activation: When the DMAC is activated automatically by reception of a message in
HCAN0’s mailbox 0 (receive-only mailbox), an interrupt request signal is not sent to the INTC.
Interrupts: When the mailbox interrupt mask register (MBIMR) is set, the interrupt register
(IRR8, 2, 1) is not set by reception completion, transmission completion, or transmission
cancellation for the set mailboxes.
Error Counters: In the case of error active and error passive, REC and TEC normally count up
and down. In the bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If
REC reaches 96 during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set.
Register Access: Byte or word access can be used on all HCAN registers. Longword access
cannot be used.
Register Initialization in Standby Modes: All HCAN registers are initialized in hardware
standby mode and software standby mode.
Differences from the HD64F7005:
Rev.2.0, 07/03, page 579 of 960