SH7055S Datasheet, PDF (318/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 2—Input Capture Interrupt Enable 0C (ICE0C): Enables or disables interrupt requests by
the input capture flag (ICF0C) in TSR0 when ICF0C is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 2: ICE0C
0
1
Description
ICI0C interrupt requested by ICF0C is disabled
ICI0C interrupt requested by ICF0C is enabled
(Initial value)
• Bit 1—Input Capture Interrupt Enable 0B (ICE0B): Enables or disables interrupt requests by
the input capture flag (ICF0B) in TSR0 when ICF0B is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 1: ICE0B
0
1
Description
ICI0B interrupt requested by ICF0B is disabled
ICI0B interrupt requested by ICF0B is enabled
(Initial value)
• Bit 0—Input Capture Interrupt Enable 0A (ICE0A): Enables or disables interrupt requests by
the input capture flag (ICF0A) in TSR0 when ICF0A is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 0: ICE0A
0
1
Description
ICI0A interrupt requested by ICF0A is disabled
ICI0A interrupt requested by ICF0A is enabled
(Initial value)
Timer Interrupt Enable Registers 1A and 1B (TIER1A, TIER1B)
TIER1A: TIER1A controls enabling/disabling of channel 1 input capture, compare-match, and
overflow interrupt requests.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
— OVE1A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit:
Bit name:
Initial value:
R/W:
7
IME1H
0
R/W
6
IME1G
0
R/W
5
IME1F
0
R/W
4
IME1E
0
R/W
3
IME1D
0
R/W
2
IME1C
0
R/W
1
IME1B
0
R/W
0
IME1A
0
R/W
Rev.2.0, 07/03, page 280 of 960