SH7055S Datasheet, PDF (799/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

(3.2) Flash multipurpose data destination parameter (FMPDR: general register R4 of CPU)
This parameter indicates the start address in the area which stores the data to be programmed
in the user MAT. When the storage destination of the program data is in flash memory, an
error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR.
Bit :
31
30
29
28
27
26
25
24
MOD31 MOD30 MOD29 MOD28 MOD27 MOD26 MOD25 MOD24
Bit :
23
22
21
20
19
18
17
16
MOD23 MOD22 MOD21 MOD20 MOD19 MOD18 MOD17 MOD16
Bit :
15
14
13
12
11
10
9
8
MOD15 MOD14 MOD13 MOD12 MOD11 MOD10 MOD9 MOD8
Bit :
7
6
5
4
3
2
1
0
MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0
Bits 31 to 0—MOD31 to MOD0: Store the start address of the area which stores the program
data for the user MAT. The consecutive 128-byte data is programmed to the user MAT starting
from the specified start address.
(3.3) Flash pass/fail parameter (FPFR: general register R0 of CPU)
This parameter indicates the return value of the program processing result.
Bit :
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit :
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Bit :
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
Bit :
7
0
6
5
4
MD
EE
FK
3
2
1
0
0
WD
WA
SF
Bits 31 to 7—Unused: Return 0.
Bit 6—Programming Mode Related Setting Error Detect (MD): Returns the check result of
whether the signal input to the FWE pin is high and whether the error protection state is entered.
When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is
written to this bit. The input level to the FWE pin and the error protection state can be confirmed
Rev.2.0, 07/03, page 761 of 960