SH7055S Datasheet, PDF (875/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

22.10.3 Storable Area for Procedure Program and Programming Data
In the descriptions in the previous section, storable areas for the programming/erasing procedure
programs and program data are assumed to be in on-chip RAM. However, the procedure
programs and data can be stored in and executed from other areas (e.g. external address space) as
long as the following conditions are satisfied.
(1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in
on-chip RAM, therefore, this area is not available for use.
(2) The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure
this area is reserved.
(3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be
executed in on-chip RAM.
(4) The flash memory is accessible until the start of programming or erasing, that is, until the
result of downloading has been judged. When in a mode in which the external address space is
not accessible, such as single-chip mode, the required procedure programs, interrupt vector
table, interrupt processing routine, and user branch program should be transferred to on-chip
RAM before programming/erasing of the flash memory starts.
(5) The flash memory is not accessible during programming/erasing operations. Therefore, the
programming/erasing program must be downloaded to on-chip RAM in advance. Areas for
executing each procedure program for initiating programming/erasing, the user program at the
user branch destination for programming/erasing, the interrupt vector table, and the interrupt
processing routine must be located in on-chip memory other than flash memory or the external
address space.
(6) After programming/erasing, access to flash memory is inhibited until FKEY is cleared.
A reset state (RES = 0) for more than at least 100 µs must be taken when the LSI mode is
changed to reset on completion of a programming/erasing operation.
Transitions to the reset state or hardware standby mode during programming/erasing are
inhibited. When the reset signal is accidentally input to the LSI, a longer period in the reset
state than usual (100 µs) is needed before the reset signal is released.
(7) Switching of the MATs by FMATS is needed for programming/erasing of the user MAT in
user boot mode. The program which switches the MATs should be executed from the on-chip
RAM. For details, see section 22.8.1, Switching between User MAT and User Boot MAT.
Please make sure you know which MAT is selected when switching the MATs.
(8) When the program data storage area indicated by the FMPDR parameter in the programming
processing is within the flash memory area, an error will occur. Therefore, temporarily
transfer the program data to on-chip RAM to change the address set in FMPDR to an address
other than flash memory.
Based on these conditions, tables 22.29 and 22.30 show the areas in which the program data can
be stored and executed according to the operation type and mode.
Rev.2.0, 07/03, page 837 of 960