SH7055S Datasheet, PDF (74/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

2.3.2 Addressing Modes
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8 Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Direct register Rn
addressing
The effective address is register Rn. (The operand —
is the contents of register Rn.)
Indirect register @Rn
addressing
The effective address is the contents of register Rn. Rn
Rn
Rn
Post-increment @Rn+
indirect register
addressing
Pre-decrement @–Rn
indirect register
addressing
The effective address is the contents of register Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
Rn
Rn
Rn
(After the
instruction
executes)
Byte: Rn + 1
→ Rn
Rn + 1/2/4 ₊
Word: Rn + 2
→ Rn
1/2/4
Longword:
Rn + 4 → Rn
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Byte: Rn – 1
→ Rn
Word: Rn – 2
→ Rn
Rn
Rn – 1/2/4 _–
1/2/4
Rn – 1/2/4
Longword:
Rn – 4 → Rn
(Instruction
executed with
Rn after
calculation)
Rev.2.0, 07/03, page 36 of 960