SH7055S Datasheet, PDF (566/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 1—Halt Request (MCR1): Controls halting of the HCAN module.
Bit 1: MCR1
0
1
Description
Normal operating mode
Halt mode transition request
(Initial value)
• Bit 0—Reset Request (MCR0): Controls resetting of the HCAN module.
Bit 0: MCR0
0
1
Description
Normal operating mode (MCR0 = 0 and GSR3 = 0)
[Setting condition]
When 0 is written after an HCAN reset
Reset mode transition request
(Initial value)
In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the
HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after
MCR0 is cleared to 0.
16.2.2 General Status Register (GSR)
The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN
bus.
Bit: 7
6
5
4
3
2
1
0
—
—
—
— GSR3 GSR2 GSR1 GSR0
Initial value: 0
0
0
0
1
1
0
0
R/W: R
R
R
R
R
R
R
R
• Bits 7 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 3—Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal
operating state or the reset state. This bit cannot be modified.
Bit 3: GSR3
0
1
Description
Normal operating state
[Setting condition]
After an HCAN internal reset
Configuration mode
[Reset condition]
MCR0-initiated reset state or sleep mode
(Initial value)
Rev.2.0, 07/03, page 528 of 960