SH7055S Datasheet, PDF (800/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter
the error protection state, see section 22.6.3, Error Protection.
Bit 6
MD
0
1
Description
FWE and FLER settings are normal (FWE = 1, FLER = 0)
FWE = 0 or FLER = 1, and programming cannot be performed
Bit 5—Programming Execution Error Detect (EE): 1 is returned to this bit when the specified
data could not be written because the user MAT was not erased or when flash-memory related
register settings are partially changed on returning from the user branch processing.
If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case,
after removing the error factor, erase the user MAT.
If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming
is performed. In this case, both the user MAT and user boot MAT are not rewritten.
Programming of the user boot MAT must be executed in boot mode or programmer mode.
Bit 5
EE
0
1
Description
Programming has ended normally
Programming has ended abnormally (programming result is not guaranteed)
Bit 4—Flash Key Register Error Detect (FK): Returns the check result of the value of FKEY
before the start of the programming processing.
Bit 4
FK
0
1
Description
FKEY setting is normal (FKEY = H'A5)
FKEY setting is error (FKEY = value other than H'A5)
Bit 3—Unused: Returns 0.
Rev.2.0, 07/03, page 762 of 960