SH7055S Datasheet, PDF (11/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Item
Page Revisions (See Manual for Details)
11.2.22 Cycle Registers (CYLR) 335
Cycle Registers (CYLR6A to
CYLR6D, CYLR7A to CYLR7D)
Description amended
At the same time, the buffer register (BFR) value is
transferred to the duty register (DTR). Output pin (TO6A
to TO6D, TO7A to TO7D) of corresponding channnel will
be 0 when H'0000 of BFR is 0 output and otherwise will
11.2.26 Channel 10 Registers 338 Description amended
Counters(TCNT)
Free-Running Counter 10AH,AL
…an input clock and is cleared to the initial value by input
capture input (TI10)(AGCK).
(TCNT10AH, TCNT10AL)
11.2.26 Channel 10 Registers 342 Description amended
Registers (TCNT)
Input Capture Register 10AH, AL
At the same time, ICF10A in timer status register 10
(TSR10) is set to 1.
(ICR10AH, ICR10AL)
11.3.1 Overview
355 Description amended
Channels 6 and 7
Do not set a value in DTR that will result in the condition
DTR > CYLR. When H'0000 is set to DTR, do not have
DTR directly read H'0000. Set BFR to H'0000 and set
H'0000 by forwarding from BFR to DTR. If H'0000 is
directly set to DTR, duty may not be 0%.
11.3.8 Twin-Capture Function 365 Description amended
Line 4
When TCNT0, TCNT1A, and TCNT2A in channel 0,
channel 1, and channel 2 are started by a setting in the
timer status register (TSR), and an edge detection is
carried out by the ICR0A input as a trigger signal, the
TCNT1A value is transferred to OSBR1, and the TCNT2A
value to OSBR2. Edge detection is as described in
section 11.3.4, Input Capture Function.
Rev.2.0, 07/03, page xi of xxxviii