SH7055S Datasheet, PDF (188/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 9.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when the T_w state shifts to the T₂ state. When using external
waits, use a WCR setting of 1 state or more when extending CS assertion, and 2 states or more
otherwise.
T₁
T_W
T_W
T_W0
T₂
CK
Address
Read
Write
Data
,
Data
Figure 9.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT
Signal Wait State)
Rev.2.0, 07/03, page 150 of 960