SH7055S Datasheet, PDF (613/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.3.6 HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 16.14 shows a flowchart of the HCAN halt mode.
MCR1 = 1
GSR2 = 1?
(Wait until transmission is
No
completed if in progress)
Bus idle?
Yes
MBCR setting
MCR1 = 0
CAN bus communication possible
: Settings by user
: Processing by hardware
Figure 16.14 HCAN Halt Mode Flowchart
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
16.3.7 Interrupt Interface
There are 12 interrupt sources for each HCAN channel. Four independent interrupt vectors are
assigned to each channel. Table 16.6 lists the HCAN interrupt sources.
With the exception of the power-on reset processing vector (IRR0), these sources can be masked.
Masking is implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask
register (IMR).
Rev.2.0, 07/03, page 575 of 960