SH7055S Datasheet, PDF (173/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Bus State Controller (BSC)
9.1 Overview
The bus state controller (BSC) divides up the address spaces and outputs control for various types
of memory. This enables memories like SRAM and ROM to be linked directly to the chip without
external circuitry, simplifying system design and enabling high-speed data transfer to be achieved
in a compact system.
9.1.1 Features
The BSC has the following features:
• Address space is divided into four spaces
 A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum 4 Mbytes
for on-chip ROM disabled mode, for address space CS0
 A maximum linear 4 Mbytes for each of address spaces CS1–CS3
 Bus width can be selected for each space (8 or 16 bits)
 Wait states can be inserted by software for each space
 Wait state insertion with WAIT pin in external memory space access
 Outputs control signals for each space according to the type of memory connected
• On-chip ROM and RAM interfaces
 On-chip RAM access of 32 bits in 1 state
 On-chip Rom access of 32 bits in 1 state for a read and 2 states for a write
Rev.2.0, 07/03, page 135 of 960