SH7055S Datasheet, PDF (398/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

counter for the relevant channel performs a cyclic count. The relevant TCNT counter is cleared by
a compare-match of TCNT with GR3D, GR4D, or GR5D in channel 3 to 5, or CYLR in channels
6 and 7 (counter clear function). TCNT starts counting up as a cyclic counter when the
corresponding STR bit in TSTR is set to 1 after the TMDR setting is made. When the count value
matches the GR3D, GR4D, GR5D, or CYLR value, the corresponding IMF3D, IMF4D, or IMF5D
bit in the timer status register (TSR) (or the CMF bit in TSR6 or TSR7 for channels 6 and 7) is set
to 1, and TCNT is cleared to H'0000 (H'0001 in channels 6 and 7).
If the corresponding TIER bit is set to 1 at this time, an interrupt request is sent to the CPU. After
the compare-match, TCNT starts counting up again from H'0000 (H'0001 in channels 6 and 7).
Figure 11.14 shows the operation when channel 3 is used as a cyclic counter (with a cycle setting
of H'0008).
Pø
TCNT3
Clock
TCNT3 ⁰⁰⁰⁸
GR3D
(period)
TSR3
IMF3D
0000
0001
0008
0002
0003
0007
0008
Cleared by software
0008
0000
0001
0002
0003
0004
0005
Cleared by software
Figure 11.14 Example of Cyclic Counter Operation
11.3.3 Compare-Match Function
Designating general registers in channels 1 to 5 and 11 (GR1A to GR1H, GR2A to GR2H, GR3A
to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) for compare-match operation in the
timer I/O control registers (TIOR1 to TIOR5, TIOR11) enables compare-match output to be
performed at the corresponding external pins (TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to
TIO3D, TIO4A to TIO4D, TIO5A to TIO5D, TIO11A, TIO11B).
A free-running counter (TCNT) starts counting up when 1 is set in the timer status register
(TSTR). When the desired number is set beforehand in GR, and the TCNT value matches the GR
value, the timer status register (TSR) bit corresponding to GR is set and a waveform is output
from the corresponding external pin.
1 output, 0 output, or toggle output can be selected by means of a setting in TIOR. If the
appropriate interrupt enable register (TIER) setting is made, an interrupt request will be sent to the
CPU when a compare-match occurs.
Rev.2.0, 07/03, page 360 of 960