SH7055S Datasheet, PDF (840/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 22.15 Commands in Programmer Mode
1st Cycle
2nd Cycle
Command
Memory
Number MAT to be
of Cycles Accessed Mode Address Command Mode Address Data
Memory-read 1+n
mode
User MAT
User boot
MAT
Write
Write
X H'00
X H'05
Read RA
Dout
Auto-program 129
mode
User MAT
User boot
MAT
Write
Write
X H'40
X H'45
Write WA
Din
Auto-erase
2
mode
User MAT
User boot
MAT
Write
Write
X H'20
X H'25
Write X
H'20
H'25
Status-read 2
mode
Common to Write
both MATs
X H'71
Write X
H'71
Notes
1. In auto-program mode, 129 cycles are required in command writing because of the
simultaneous 128-byte write.
2. In memory read mode, the number of cycles varies with the number of address writing
cycles (n).
3. In an automatic erasure command, input the same command code for the 1st and 2nd
cycles (for erasing of the user boot MAT, input H'25 for the 1st and 2nd cycles).
22.9.3 Memory-Read Mode
(1) On completion of automatic programming, automatic erasure, or status read, the LSI enters a
command input wait state. So, to read the contents of memory after these operations, issue the
command to transit to memory-read mode before reading from the memory.
(2) In memory-read mode, the writing of commands is possible in the same way as in command
input wait state.
(3) After entering memory-read mode, continuous reading is possible.
(4) After power has first been supplied, the LSI enters memory-read mode of the user MAP.
For the AC characteristics in memory read mode, see section 22.10.2, AC Characteristics and
Timing in programmer Mode.
Rev.2.0, 07/03, page 802 of 960