SH7055S Datasheet, PDF (107/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

3.5 Synchronization with CPU
Synchronization with CPU: Floating-point instructions and CPU instructions are executed in
turn, according to their order in the program, but in some cases operations may not be completed
in the program order due to a difference in execution cycles. When a floating-point instruction
accesses only FPU resources, there is no need for synchronization with the CPU, and a CPU
instruction following an FPU instruction can finish its operation before completion of the FPU
operation. Consequently, in an optimized program, it is possible to effectively conceal the
execution cycle of a floating-point instruction that requires a long execution cycle, such as a
divide instruction. On the other hand, a floating-point instruction that accesses CPU resources,
such as a compare instruction, must be synchronized to ensure that the program order is observed.
Floating-Point Instructions That Require Synchronization: Load, store, and compare
instructions, and instructions that access the FPUL or FPSCR register, must be synchronized
because they access CPU resources. Load and store instructions access a general register. Post-
increment load and pre-decrement store instructions change the contents of a general register. A
compare instruction modifies the T bit. An FPUL or FPSCR access instruction references or
changes the contents of the FPUL or FPSCR register. These references and changes must all be
synchronized with the CPU.
3.6 Usage Notes
1. When using the FPU (using FPU instructions or FPU-related CPU instructions)
a. Limitations on using the BT and BF instructions on the SH7055F are abolished.
The BT and BF instructions can be used on the SH7055SF.
b. The branch destination of TRAP instruction and interrupt/exception handling must be
located at a 4n address. In this case, do not place an FPU instruction or FPU-related CPU
instruction at address 4n or 4n+2.
2. When not using the FPU (not using FPU instructions or FPU-related CPU instructions)
After a power-on reset, the FPU should be placed in the module standby state until a DMAC or
AUD bus cycle is generated.
Specifically, write 1 to bit 1 in the module standby control register.
This operation is also effective in reducing current dissipation.
When the FPU enters the module standby state, any subsequent FPU instruction or FPU-
related CPU instruction will be subjected to exception handling as an illegal instruction.
3. Restrictions of the FADD and FSUB instructions
In this FPU, values calculated by the following two arithmetic operations with a special
operand have a sign which is different from values’ expected in the IEEE Standard 754.
1) FADD FRm, FRn
FRm = –INF(0xFF80000)
FRn = MAX(0x7F7FFFFF)
Rev.2.0, 07/03, page 69 of 960