SH7055S Datasheet, PDF (218/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

10.3.6 Bus Modes
Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes:
cycle-steal and burst.
Cycle-Steal Mode: In cycle-steal mode, the bus right is given to another bus master after each
one-transfer-unit (8-bit, 16-bit, or 32-bit) DMAC transfer. When the next transfer request occurs,
the bus right is obtained from the other bus master and a transfer is performed for one transfer
unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until
the transfer end conditions are satisfied.
Cycle-steal mode can be used with all categories of transfer destination, transfer source and
transfer request. Figure 10.8 shows an example of DMA transfer timing in cycle-steal mode.
Bus control returned to CPU
Bus cycle
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU
Read/Write
Read/Write
Figure 10.8 DMA Transfer Timing Example in Cycle-Steal Mode
Burst Mode: Once the bus right is obtained, transfer is performed continuously until the transfer
end condition is satisfied.
Figure 10.9 shows an example of DMA transfer timing in burst mode.
Bus cycle
CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Read/Write Read/Write Read/Write
Figure 10.9 DMA Transfer Timing Example in Burst Mode
Rev.2.0, 07/03, page 180 of 960