SH7055S Datasheet, PDF (382/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Correction Counter Clear Register 10 (TCCLR10): Correction counter clear register 10
(TCCLR10) is a 16-bit readable/writable register.
TCCLR10 is constantly compared with TCNT10F, and when the two values match, TCNT10F
halts. TCNTxx can be cleared at this time by setting TRGxxEN (xx = 1A, 1B, 2A, 2B) in TCR10.
Then, when TCNT10D is H'00 and TI10 is input, TCNT10F is cleared to H'0001.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCCLR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and
software standby mode.
Noise Canceler Registers
There are two 8-bit noise canceler registers in channel 10: TCNT10H and NCR10.
Channel
10
Abbreviation
TCNT10H
NCR10
Function
Noise canceler counter
Noise canceler compare-match register
(Initial value H'00)
(Initial value H'FF)
Noise Canceler Counter 10H (TCNT10H): Noise canceler counter 10H (TCNT10H) is an 8-bit
readable/writable register. When the noise canceler function is enabled, TCNT10H starts counting
up on Pφ × 10, with the signal from external input (TI10) (AGCK) as a trigger. The counter
operates even if STR10 is cleared to 0 in the timer start register (TSTR1). TI10 input is masked
while the counter is running. When the count matches the noise canceler register (NCR10) value,
the counter is cleared and TI10 input masking is released.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
TCNT10H is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Rev.2.0, 07/03, page 344 of 960